{"id":5536,"date":"2024-02-08T05:36:15","date_gmt":"2024-02-08T05:36:15","guid":{"rendered":"https:\/\/vitbangalore.in\/life\/?page_id=5536"},"modified":"2024-05-30T03:04:21","modified_gmt":"2024-05-30T03:04:21","slug":"risc-v-rtl-verification","status":"publish","type":"page","link":"https:\/\/vitbangalore.in\/life\/risc-v-rtl-verification\/","title":{"rendered":"RISC-V RTL VERIFICATION"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-page\" data-elementor-id=\"5536\" class=\"elementor elementor-5536\">\n\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-d81d396 e-flex e-con-boxed e-con e-parent\" data-id=\"d81d396\" data-element_type=\"container\" data-settings=\"{&quot;content_width&quot;:&quot;boxed&quot;}\" data-core-v316-plus=\"true\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t<div class=\"elementor-element elementor-element-4ccf0f1 elementor-drop-cap-yes elementor-drop-cap-view-default elementor-widget elementor-widget-text-editor\" data-id=\"4ccf0f1\" data-element_type=\"widget\" data-settings=\"{&quot;drop_cap&quot;:&quot;yes&quot;}\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.17.0 - 08-11-2023 *\/\n.elementor-widget-text-editor.elementor-drop-cap-view-stacked .elementor-drop-cap{background-color:#69727d;color:#fff}.elementor-widget-text-editor.elementor-drop-cap-view-framed .elementor-drop-cap{color:#69727d;border:3px solid;background-color:transparent}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap{margin-top:8px}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap-letter{width:1em;height:1em}.elementor-widget-text-editor .elementor-drop-cap{float:left;text-align:center;line-height:1;font-size:50px}.elementor-widget-text-editor .elementor-drop-cap-letter{display:inline-block}<\/style>\t\t\t\t<p><strong>RISC-V RTL Verification <\/strong> Program trains working professionals extensively on the Verification methodologies and helps them to upgrade their skills as an ASIC Verification Engineer.<\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-312dec7 elementor-drop-cap-yes elementor-drop-cap-view-default elementor-widget elementor-widget-text-editor\" data-id=\"312dec7\" data-element_type=\"widget\" data-settings=\"{&quot;drop_cap&quot;:&quot;yes&quot;}\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<p><b>Why Choose a UVM For Verification?<\/b><\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-473bb98 elementor-widget elementor-widget-text-editor\" data-id=\"473bb98\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<p>The Online RISC-V RTL VLSI Verification starts with Verification Methodologies overview, offering hands on experience with various verification methodologies such as Constraint Random Coverage Driven Verification (CRCDV), Assertion Based Verification (ABV) using the languages like SystemVerilog and Methodologies like UVM on the project life cycle from Verification planning to Verification signoff, making the trainees industry ready. And also, this program offers understanding on RISC-V ISA and hands on experience on Verification methodology for verifying the RISC-V based designs and achieve coverage closure.<\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-5d3b265 elementor-drop-cap-yes elementor-drop-cap-view-default elementor-widget elementor-widget-text-editor\" data-id=\"5d3b265\" data-element_type=\"widget\" data-settings=\"{&quot;drop_cap&quot;:&quot;yes&quot;}\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<p><strong>Prerequisite:<\/strong> Verilog Concepts<br \/><strong>Learning Mode:<\/strong> Blended (Pre-Recorded + Live Q &amp; A)<br \/><strong>Course Duration:<\/strong> 6 Months<br \/><strong>EDA Tool:<\/strong> Siemens \u2013 Questasim<br \/>C<strong>ourse Fees:<\/strong> Rs.60, 000\/- (Inc. GST)<\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-57c0103 elementor-widget elementor-widget-text-editor\" data-id=\"57c0103\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<p><strong>Key Highlights<\/strong><\/p><ul><li>Industry-Standard Curriculum<\/li><li>Blended course with Support Material, Labs, and Projects<\/li><li>Course Delivered by Industry Experts<\/li><li>Live Q&amp;A and Review Sessions<\/li><li>Mobile Apps \u2013 Attend Anywhere Anytime<\/li><li>Certificate on successful completion of the course<\/li><li>24*7 VPN Access<\/li><\/ul>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-25a0fe2 elementor-widget elementor-widget-text-editor\" data-id=\"25a0fe2\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<p><strong>Programme Modules<\/strong><\/p>\n<ul>\n<li>Advanced Verilog &amp; Code Coverage<\/li>\n<li>Verification Methodology overview<\/li>\n<li>SV Language concepts &#8211; Datatypes, Memories, Interface &amp; clocking block, Randomization, OOP<\/li>\n<li>Systemverilog Assertions<\/li>\n<li>UVM Methodology Concepts &#8211;<\/li>\n<li>Factory, Phases, Ports, Configuration, Sequences<\/li><li>2 Pilot Project&#8217;s ( SV &amp; UVM)<\/li>\n<li>Industry Standard Project &#8211; RISC-V processor Verification<\/li>\n<\/ul>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-529ad1a elementor-widget elementor-widget-text-editor\" data-id=\"529ad1a\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<p>For detailed Curriculum<\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-9e88f4d e-flex e-con-boxed e-con e-parent\" data-id=\"9e88f4d\" data-element_type=\"container\" data-settings=\"{&quot;content_width&quot;:&quot;boxed&quot;}\" data-core-v316-plus=\"true\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t<div class=\"elementor-element elementor-element-9b9b3aa elementor-widget elementor-widget-button\" data-id=\"9b9b3aa\" data-element_type=\"widget\" data-widget_type=\"button.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div class=\"elementor-button-wrapper\">\n\t\t\t<a class=\"elementor-button elementor-button-link elementor-size-sm\" href=\"https:\/\/vitbangalore.in\/life\/wp-content\/uploads\/2024\/03\/RISC-V-RTL-Verification-Course.pdf\" target=\"_blank\">\n\t\t\t\t\t\t<span class=\"elementor-button-content-wrapper\">\n\t\t\t\t\t\t<span class=\"elementor-button-icon elementor-align-icon-left\">\n\t\t\t\t<i aria-hidden=\"true\" class=\"fas fa-download\"><\/i>\t\t\t<\/span>\n\t\t\t\t\t\t<span class=\"elementor-button-text\">Click to Download<\/span>\n\t\t<\/span>\n\t\t\t\t\t<\/a>\n\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-ac717b4 e-flex e-con-boxed e-con e-parent\" data-id=\"ac717b4\" data-element_type=\"container\" data-settings=\"{&quot;content_width&quot;:&quot;boxed&quot;}\" data-core-v316-plus=\"true\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t<div class=\"elementor-element elementor-element-dcf9057 elementor-widget elementor-widget-image\" data-id=\"dcf9057\" data-element_type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.17.0 - 08-11-2023 *\/\n.elementor-widget-image{text-align:center}.elementor-widget-image a{display:inline-block}.elementor-widget-image a img[src$=\".svg\"]{width:48px}.elementor-widget-image img{vertical-align:middle;display:inline-block}<\/style>\t\t\t\t\t\t\t\t\t\t\t\t<img decoding=\"async\" src=\"https:\/\/vitbangalore.in\/life\/wp-content\/uploads\/elementor\/thumbs\/Sample-Certificate-qltna2d19zzajicas5nmw3v2btkwujp4awyh8raxgo.png\" title=\"Sample Certificate\" alt=\"Sample Certificate\" loading=\"lazy\" \/>\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-3ab593a e-flex e-con-boxed e-con e-parent\" data-id=\"3ab593a\" data-element_type=\"container\" data-settings=\"{&quot;content_width&quot;:&quot;boxed&quot;}\" data-core-v316-plus=\"true\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t<div class=\"elementor-element elementor-element-dd9d139 elementor-widget elementor-widget-spacer\" data-id=\"dd9d139\" data-element_type=\"widget\" data-widget_type=\"spacer.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.17.0 - 08-11-2023 *\/\n.elementor-column .elementor-spacer-inner{height:var(--spacer-size)}.e-con{--container-widget-width:100%}.e-con-inner>.elementor-widget-spacer,.e-con>.elementor-widget-spacer{width:var(--container-widget-width,var(--spacer-size));--align-self:var(--container-widget-align-self,initial);--flex-shrink:0}.e-con-inner>.elementor-widget-spacer>.elementor-widget-container,.e-con>.elementor-widget-spacer>.elementor-widget-container{height:100%;width:100%}.e-con-inner>.elementor-widget-spacer>.elementor-widget-container>.elementor-spacer,.e-con>.elementor-widget-spacer>.elementor-widget-container>.elementor-spacer{height:100%}.e-con-inner>.elementor-widget-spacer>.elementor-widget-container>.elementor-spacer>.elementor-spacer-inner,.e-con>.elementor-widget-spacer>.elementor-widget-container>.elementor-spacer>.elementor-spacer-inner{height:var(--container-widget-height,var(--spacer-size))}.e-con-inner>.elementor-widget-spacer.elementor-widget-empty,.e-con>.elementor-widget-spacer.elementor-widget-empty{position:relative;min-height:22px;min-width:22px}.e-con-inner>.elementor-widget-spacer.elementor-widget-empty .elementor-widget-empty-icon,.e-con>.elementor-widget-spacer.elementor-widget-empty .elementor-widget-empty-icon{position:absolute;top:0;bottom:0;left:0;right:0;margin:auto;padding:0;width:22px;height:22px}<\/style>\t\t<div class=\"elementor-spacer\">\n\t\t\t<div class=\"elementor-spacer-inner\"><\/div>\n\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>RISC-V RTL Verification Program trains working professionals extensively on the Verification methodologies and helps them to upgrade their skills as an ASIC Verification Engineer. Why Choose a UVM For Verification? The Online RISC-V RTL VLSI Verification starts with Verification Methodologies overview, offering hands on experience with various verification methodologies such as Constraint Random Coverage Driven [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"elementor_header_footer","meta":{"footnotes":""},"class_list":["post-5536","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/vitbangalore.in\/life\/wp-json\/wp\/v2\/pages\/5536","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/vitbangalore.in\/life\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/vitbangalore.in\/life\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/vitbangalore.in\/life\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/vitbangalore.in\/life\/wp-json\/wp\/v2\/comments?post=5536"}],"version-history":[{"count":47,"href":"https:\/\/vitbangalore.in\/life\/wp-json\/wp\/v2\/pages\/5536\/revisions"}],"predecessor-version":[{"id":5970,"href":"https:\/\/vitbangalore.in\/life\/wp-json\/wp\/v2\/pages\/5536\/revisions\/5970"}],"wp:attachment":[{"href":"https:\/\/vitbangalore.in\/life\/wp-json\/wp\/v2\/media?parent=5536"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}