RISC-V RTL VERIFICATION
RISC-V RTL Verification Program trains working professionals extensively on the Verification methodologies and helps them to upgrade their skills as an ASIC Verification Engineer.
Why Choose a UVM For Verification?
The Online RISC-V RTL VLSI Verification starts with Verification Methodologies overview, offering hands on experience with various verification methodologies such as Constraint Random Coverage Driven Verification (CRCDV), Assertion Based Verification (ABV) using the languages like SystemVerilog and Methodologies like UVM on the project life cycle from Verification planning to Verification signoff, making the trainees industry ready. And also, this program offers understanding on RISC-V ISA and hands on experience on Verification methodology for verifying the RISC-V based designs and achieve coverage closure.
Prerequisite: Verilog Concepts
Learning Mode: Blended (Pre-Recorded + Live Q & A)
Course Duration: 6 Months
EDA Tool: Siemens – Questasim
Course Fees: Rs.60, 000/- (Inc. GST)
Key Highlights
- Industry-Standard Curriculum
- Blended course with Support Material, Labs, and Projects
- Course Delivered by Industry Experts
- Live Q&A and Review Sessions
- Mobile Apps – Attend Anywhere Anytime
- Certificate on successful completion of the course
- 24*7 VPN Access
Programme Modules
- Advanced Verilog & Code Coverage
- Verification Methodology overview
- SV Language concepts – Datatypes, Memories, Interface & clocking block, Randomization, OOP
- Systemverilog Assertions
- UVM Methodology Concepts –
- Factory, Phases, Ports, Configuration, Sequences
- 2 Pilot Project’s ( SV & UVM)
- Industry Standard Project – RISC-V processor Verification
For detailed Curriculum
